An alternating-current surface-discharge panel representative of a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells that are formed between the front plate and the rear plate faced to each other. For the front plate, a plurality of display electrode pairs, each made of a scan electrode and a sustain electrode, are formed on a front glass substrate in parallel with each other. A dielectric layer and a protective layer are formed to cover these display electrode pairs. For the rear plate, a plurality of parallel data electrodes are formed on a rear glass substrate and a dielectric layer is formed over the data electrodes to cover them. Further, a plurality of barrier ribs are formed on the dielectric layer in parallel with the data electrodes. Phosphor layers are formed over the surface of the dielectric layer and the side faces of the barrier ribs. The front plate and the rear plate are faced to each other and sealed together so that the display electrode pairs intersect with data electrodes. A discharge gas containing xenon in a partial pressure ratio of 5%, for example, is charged in the inside discharge space formed between the plates. Discharge cells are formed in portions where the display electrode pairs are faced to the data electrodes. For a panel formed as above, gas discharge generates ultraviolet light in each discharge cell. This ultraviolet light excites the red (R), green (G), and blue (G) phosphors so that the phosphors emit the corresponding colors for color display.
A general method for driving a panel is a subfield method: one field is divided into a plurality of subfields and combinations of light-emitting subfields provide gradation display. Each subfield has an initializing period, an address period, and a sustain period. In the initializing period, initializing discharge is caused to form wall charges necessary for the succeeding address operation on the respective electrodes and to generate priming particles (priming for discharge=excitation particles) for causing stable address discharge. In the address period, an address pulse voltage is applied selectively to the discharge cells to be lit so that address discharge is caused and wall charges are formed (hereinafter, this operation being also referred to as “addressing”). In the sustain period, a sustain pulse voltage is applied alternately to the scan electrode and the sustain electrode forming each display electrode pair, to cause sustain discharge in the discharge cells having generated address discharge and to cause light emission of the phosphor layers in the corresponding discharge cells. Thus, an image is displayed.
The driving method is described hereinafter in the subfield methods. Initializing discharge is caused by a gently changing voltage and the initializing discharge is selectively caused in the discharge cells which have executed sustain discharge. Thus, the light emission unrelated to gradation display is minimized and the contrast ratio is improved.
Specifically, in the initializing period of one subfield out of a plurality of subfields, an all-cell initializing operation for causing initializing discharge in all the discharge cells is performed. In the initializing periods of the other subfields, a selective initializing operation for causing initializing discharge only in the discharge cells having generated sustain discharge in the preceding sustain period is performed. In this driving method, the luminance of the area displaying a black picture (hereinafter, “black picture level”) that changes depending on the light emission unrelated to image display is only due to the weak light emission caused by the all-cell initializing operation. Thus, an image having a high contrast can be displayed (see Patent Document 1, for example).
Further, above Patent Document 1 includes the descriptions of so-called erasing discharge using a narrow width pulse. In this erasing discharge, the width of the last sustain pulse in the sustain period is set shorter than the width of the other sustain pulses so that the electric potential difference between the electrodes of each display electrode pair caused by the wall charges thereon is alleviated. This erasing discharge using a narrow pulse can stabilize the address operation in the address period of the succeeding subfield. Thus, a plasma display device providing a high contrast ratio can be implemented.
Another technique is disclosed. For this technique, in each sustain period, after application of sustain pulses to the display electrode pairs are completed, an increasing ramp voltage is applied to the sustain electrodes to erase the wall charges in the discharge cells (see Patent Document 2, for example).
Still another technique is disclosed. For this technique, in each sustain period, after application of sustain pulses to the display electrode pairs are completed, a ramp voltage increasing to and kept at a predetermined value for a predetermined time period is applied to the scan electrodes, and thereafter an increasing ramp voltage is applied to the sustain electrodes. Thus, the wall charges in the discharge cells are erased (see Patent Document 3, for example).
Yet another technique is disclosed. For this technique, in each sustain period, after application of sustain pulses to the display electrode pairs are completed, an increasing ramp voltage is applied to the scan electrodes so that the gradient of the ramp voltage is changed according to the average luminance of a display image. Thus, the wall charges in the discharge cells are erased (see Patent Document 4, for example).
However, each of the techniques described in Patent Document 2 and Patent Document 3 requires a circuit for generating the ramp voltage to be applied to the sustain electrodes. The technique described in Patent Document 4 requires a circuit for changing the gradient of the ramp voltage. In each of these techniques, the size of the circuit is increased.
In recent years, with compliance of panels with higher definition, further miniaturization of discharge cells has been actively promoted. It is confirmed that so-called “charge decreasing”, a phenomenon of wall charge loss, is likely to occur in the miniaturized discharge cells. The charge decreasing poses problems, such as occurrence of discharge failure resulting in deterioration of the image display quality, and an increase in the applied voltage necessary for causing discharge.
One of the major causes for occurrence of charge decreasing is a variation in the discharge in address operation. For example, if a large variation in the discharge in address operation causes strong address discharge, in some portions where a discharge cell to be lit is adjacent to a discharge cell to be unlit, the discharge cell to be lit deprives the discharge cell to be unlit of wall charges. This phenomenon causes charge decreasing.
For this reason, generating address discharge as stably as possible is important in preventing charge decreasing.
On the other hand, in recent years, further increases in the screen size and definition of a panel have actively been promoted. Accordingly, the drive impedance of the panel tends to increase. At high drive impedance, waveform distortion, such as ringing, is likely to occur in the drive waveform generated in the driving circuit of the panel. The above erasing discharge using a narrow width pulse is intended for stabilizing the address operation in the succeeding subfield. If a waveform distortion occurs in the drive waveform for generating this erasing discharge using a narrow pulse, the erasing discharge using a narrow width pulse can be generated strongly. In such a case, it is difficult to stabilize generation of the succeeding address discharge.
Further, with recent increases in the screen size, luminance, and definition of a panel, further improvement of the image display quality has been requested of the plasma display device.    [Patent Document 1] Japanese Patent Unexamined Publication No. 2000-242224    [Patent Document 2] Japanese Patent Unexamined Publication No. 2004-348140    [Patent Document 3] Japanese Patent Unexamined Publication No. 2005-141224    [Patent Document 4] Japanese Patent Unexamined Publication No. 2003-5700